This invention is designed to combine in either a logical AND or a logical NAND function, as desired, a large number of logical input signals. This invention has many applications and is particularly useful in the output stages of programmable array logic circuitry.
Integrated circuit manufacturers are placed in a difficult position. Each customer would like to have an integrated circuit tailored to serve the specific needs of their particular product. However, a wide range of products, that is a product tailored to each customer's demand, requires a large investment in expensive production facilities. It is therefore highly desirable to provide relatively few types of devices, each of which will serve the needs of a large number of specific applications. A partial solution to this problem is the use of programmable integrated circuits. One such programmable integrated circuit is the programmable array logic circuit disclosed by Birkner, et al. in U.S. Pat. No. 4,124,899, which is assigned to Monolithic Memories, Inc., the assignee of this application, and which is hereby incorporated by reference. A programmable array is a circuit designed to accept a large number of logical input signals and programmably combine those input signals according to the rules of boolean arithmetic in order to provide a logical output signal which is the result of those boolean arithmetic operations. The programmable array disclosed by Birkner, et al., also includes a register for holding the boolean arithmetic results and applying the results as selected input signals to the programmable array, thus allowing the programmable array logic circuit to perform dynamic (i.e., time function) boolean operations. Such circuitry is designed in order that it may be tailored to the customer's specific needs by customer programming after the manufacture of the device. Many programmable arrays are programmed by using fuses between the logical input leads and the internal gates of the device. The fuses are selectively opened so as to disconnect certain logical input leads from specific gates and to leave selected logical input leads connected to specific logical gates.
Such programmable arrays create some problems. An array usually entails combining a large number of logical input signals to create one or more logical output signals. Thus a logical gate used in a programmable array must be capable of receiving a large number of input signals. This is one problem addressed by this invention. In addition, it is desirable that logical gates in programmable array circuits be capable of producing either an output signal or the inverse of that output signal and, when several of the gates are included on a single integrated circuit, it is desirable to be able to program each one of these several gates to operate as a NAND or AND gate. A prior art example of a circuit which programmably inverts an input signal is shown in Edwards, U.S. Pat. No. 4,157,480, and is shown in FIG. 1. Edwards shows Exclusive-OR gate 31 having one input lead 37 connected to a programming means (voltage supply +V, resistor 36, and programming fuse 33) for producing a logical 1 or a logical 0, another input lead 38 connected to an input node 40 for receiving an input signal, and an output lead 32. One method of providing a programmable array circuit capable of receiving a large number of input signals and providing output signals of programmable polarity is to connect the output lead of a logical gate, such as an AND gate capable of combining a large number of logical input signals, to the input node of the programmable polarity circuit 30. However, such a circuit is dependent upon the use of Exclusive-OR gate circuitry which is relatively slow, as is the Edwards circuit itself. One prior art embodiment of a two input lead Exclusive-NOR gate 10 is shown in the schematic diagram of FIG. 2. In order to switch the Exclusive-NOR gate 10 of FIG. 2 from a logical one output signal to a logical 0 output signal, (where a logical 1 output signal is a high voltage close to the positive voltage source for the circuit and a logical 0 output signal is a low voltage close to the reference potential or ground), the input signals on input leads 11 and 20 must pull the emitter of one of transistors 12 and 13 from a logical 1 to a logical 0. To accomplish this, Exclusive-NOR gate 10 must discharge the capacitor formed by the relatively large base-emitter junction of the selected transistor. Discharging a capacitor requires a certain amount of time proportional to the size of the capacitor and the resistance of the discharge path. Thus transition from a logical 1 output signal to a logical 0 output signal is relatively slow, requiring approximately 5 nanoseconds using bipolar Schottky technology. In addition, the circuit disclosed in Edwards does not provide a method for testing the programmable inverter without destroying programming fuse 33.